1. Field of the Invention
The present invention relates to a VFO device, and more particularly to a digital VFO device whereby the data can be read without retrying of reading even when a read error is occurred in reading data from a floppy disc drive device.
2. Description of the Prior Art
Variable Frequency Oscillator (hereinafter, referred to as xe2x80x9cVFOxe2x80x9d) is well known particularly as one used for regenerating data of magnetic recording disc. This VFO is generally embodied using an analog circuit. Adjusting the values of resistors or capacitors must be carried out for the analog circuit, thereby complicating the design process. It is therefore well known that in designing an integrated circuit for the analog circuit, it is difficult to decrease the chip area of the integrated circuit.
It is also a well-known fact that the digitalization of VFO has been demanded recently with the development in digital techniques. For instance, in order to meet the demand, a first prior art VFO was disclosed through a Japanese Patent Laid-Open No. H3-227123 (a prior art document), which is digitalized by using a counter.
In the first prior art VFO circuits, every time a regenerated data is occurred, the value of counter is set to 6 so that the regenerated data is positioned in the center of High level width or Low level width of a output clock signal, whereby the phase correction is performed. For this reason, in case where the regenerated data includes a peak shift, which is a characteristic of magnetically recorded data, a wrong correction is performed, causing a problem that the data cannot be exactly regenerated.
FIG. 2 shows an example where the wrong correction is performed to a pair of peak shifts in the configuration of the first prior art VFO. In FIG. 2, the output clock signal shown in bold line represents the waveform when the wrong correction is carried out, and the output clock signal shown in dotted line represents the waveform when the correction is not carried out. It is assumed that data to be regenerated is xe2x80x9c11xe2x80x9d and peak shifts are occurred, where the two bits are spaced left and right from the center, respectively.
It is a general rule that the output clock signal must be output in High level timing when a regenerated data is generated as in case at a time t10 in FIG. 1. In the configuration of the prior art VFO shown in FIG. 1, in case where the peak shift is occurred, the regenerated data at a time t11 gets out of the High level timing of the output clock signal.
The above-mentioned prior art document further disclosed a second prior art VFO that overcomes the drawback in the first prior art.
This second prior art VFO changes only the period of WINDOW pulse according to the frequency difference detected based on the phase difference. Being different from the first prior art VFO that directly substitutes the count value, the second prior art VFO is not responsive to each bit, thereby not causing a wrong correction to the peak shift.
However, because this second prior art VFO is based on accumulation of phase difference for detecting the period, it cannot be sure that the period error is accurately detected.
FIG. 3 shows the configuration of the second prior art VFO that was disclosed in the prior art document. And FIG. 4 shows an example of a wrong frequency correction performed by this second prior art VFO.
Referring to FIGS. 3 to 4, in the second prior art VFO, an input data 94 is always positioned on the right of the center, with respect to an output data 99, so that the output of a phase difference detecting circuit 95 always becomes positive, and a frequency difference detecting circuit 96 accumulates this output of the circuits 95 and permits a frequency division ratio setting circuit 97 to carry out a setting for extending the frequency.
However, the input data 94 actually has a frequency shorter than the output clock signal 99, and it moves toward the center little by little from the right end of the output clock signal 99 as shown in FIG. 4. Consequently, it becomes wrong correction.
Like this, the two problems of peak shift and frequency error conflict with each other, and there have been suggested a few correction algorithms effective in coping with one of the two problems, but not with both the problems.
The present invention has been made in view of the problems of the prior arts and its object is to provide a novel digital VFO device which comprises one VFO circuit having a function of peak shift correction and another VFO circuit having a function of frequency error correction, that is, VFO circuits having different correcting characteristic, so as to enable reading data without its retry even when a read error is occurred in reading data from the floppy disc drive device.
In order to achieve the object, the present invention provides a digital VFO device outputting, as output signal, a window signal in a predetermined phase relation to an input data having a peak shift, the digital VFO device comprising:
a plurality of VFO circuits which receives the input data having the peak shift and outputs a signal representing a peak shift state of the input data;
a synchronous counter which is provided to each of the plurality of VFO circuits and has a correcting characteristic different from each other; and
an adjusting circuit which selects one of the VFO circuits based on the signal representing the peak shift state of the input data, and outputs a correcting instruction signal to substitute a counter value of the synchronous counter of the selected VFO circuit for the synchronous counter of the other VFO circuit so as to correct the synchronous counter of the other VFO circuit,
wherein the adjusting circuit comprises:
a data storaging circuit which is provided for each of the plurality of VFO circuits and storages a signal representing a peak shift state of a first input data which is input just before a second input data;
a detecting circuit which is provided for each of the VFO circuits to detect whether a peak shift of the second input data complies with a predetermined logic, based on both a data being storaged in the data storaging circuit and a signal representing a peak shift state of the second input data, and to output the correcting instruction signal to correct the counter value of the corresponding VFO circuit when it is detected not to comply with the predetermined logic; and
a window pulse selecting circuit which selects one of the plurality of VFOs based on the detection result of the detecting circuit, and outputs, as an output signal, a WINDOW pulse of the selected VFO circuit.
Further, in order to achieve the object, the present invention provides a digital VFO device outputting, as output signal, a window signal in a predetermined phase relation to an input data having a peak shift, the digital VFO device comprising:
a plurality of VFO circuits which receives the input data having the peak shift and outputs a signal representing a peak shift state of the input data;
a synchronous counter which is provided to each of the plurality of VFO circuits and has a correcting characteristic different from each other; and
an adjusting circuit which selects one of the VFO circuits based on the signal representing the peak shift state of the input data, and outputs a correcting instruction signal to substitute a counter value of the synchronous counter of the selected VFO circuit for the synchronous counter of the other VFO circuit so as to correct the synchronous counter of the other VFO circuit, wherein the adjusting circuit comprises:
a first data storaging circuit which is provided for each of the plurality of VFO circuits and storages a signal representing a peak shift state of a first input data which is input just before a second input data;
a second data storaging circuit which is provided for each of the plurality of VFO circuits and further maintains a signal representing a peak shift state of an input data just before the data being storaged in the firsts data storaging circuit;
a detecting circuit which is provided for each of the VFO circuits to detect whether a peak shift of the second input data complies with a predetermined logic, based on both a data being storaged in the first and second data storaging circuit and a signal representing a peak shift state of the second input data, and to output the correcting instruction signal to correct the counter value of the corresponding VFO circuit when it is detected not to comply with the predetermined logic; and
a window pulse selecting circuit which selects one of the plurality of VFOs based on the detection result of the detecting circuit, and outputs, as an output signal, a WINDOW pulse of the selected VFO circuit. The present invention can be applied to various preferred types of digital VFOs as follows.
That is, the present invention may provide a digital VFO device, wherein one of the plurality of VFO circuits has priority, and when the detecting circuit does not output the detection result, a WINDOW pulse output from the VFO circuit having priority is output as the output signal.
Further, the present invention may provide a digital VFO device, wherein the signal representing the state of the peak shift of the input data includes at least a bit representing a right-shifted state of a clock signal, a bit representing a left-shifted state of a clock signal, a bit representing a right-shifted state of a data signal, and a bit representing a left-shifted state of a data signal.
In addition, the present invention may provide a digital VFO device, wherein the output of the input data from the device is delayed by one system clock of the device, and also the output of the WINDOW pulse is delayed by one system clock of the device.